1. Field of the Invention
The present invention relates to a semiconductor device memory, and more particularly, to a semiconductor memory device and a test method thereof capable of more stably and effectively performing a wafer test of the semiconductor memory device having a small pad size and a small interval between pads.
2. Description of the Related Art
Generally, a test process of a semiconductor memory device can be classified into a wafer test performed before a wafer is assembled and a package test performed in a package state after assembly. The wafer test can be classified into a pre-laser test performed before a laser repair process and an electronic die sorting (EDS) test performed after the laser repair process.
In particular, since the wafer test is performed in a wafer state before assembly, a tool called a “probe” should be in direct contact with a pad on a die. Generally, the probe has a plurality of needle-shaped pins disposed at predetermined intervals corresponding to pads.
Specifically, a probe card includes a plurality of probes, and the probes simultaneously contact the plurality of pads of the semiconductor memory device to input a necessary test signal and detect an output signal, so that it is determined whether or not the semiconductor memory device is good or bad on the basis of the detection of the output signal.
Meanwhile, maintaining a high bandwidth of the semiconductor memory device is still necessary. It is especially necessary to increase the number of input/output data bits corresponding to the number of simultaneously accessible data pins in order to increase a system operating speed of a semiconductor memory device for a mobile electronic appliance. In particular, fully independently operating command pins or input/output data pins should be implemented in a single semiconductor chip. Therefore, expansion of the input/output data bits makes it difficult to reduce a chip size and fabricate a package.
For example, in the case of a ball grid array (BGA) package, when the input/output data bit number is 256 bits, more than 500 ball-outs are required to fabricate the package. However, since the currently used BGA package has 225-460 pins, it is almost impossible to fabricate a package including 500 ball-outs or more.
In particular, since it is unmarketable to employ the BGA package to a semiconductor memory device for a mobile electronic appliance requiring a small package, new package manufacturing technologies, for example, p-bump (micro bump) technology, and so on, have been developed.
Micro bump technology is a pad fabricating technology for directly connecting pads without interconnections by parallely positioning both sides of pads to correspond to interface signals required between both chips, using the fact that a controller semiconductor chip of a mobile electronic appliance accesses a semiconductor memory device chip in a point-to-point manner.
As a result, it is possible to reduce a pad pitch, i.e., an interval between pads. However, when the wafer of the semiconductor memory device fabricated as described above is tested, it can be impossible to perform the pad probing.
Specifically, a needle of a probe has a thickness of about 15 μm, and an error of about 5 μm or more is generated during positioning of the probe. When the probe needle inappropriately contacts the pad, a contact error is generated, thereby making it difficult to properly perform the test. As a result, when the pad has a width or length of 35 μm or less, it is difficult to obtain a secure contact, and when the pad pitch, i.e., an interval between pads, is smaller than 50 μm, the probe needle could be in bad contact with adjacent pads.
Therefore, when the circuit integration density of the semiconductor memory device increases to reduce a chip size, a pad size and a pad pitch should be reduced corresponding to a reduction of the semiconductor chip size.
FIG. 1 illustrates a configuration for a wafer test of a semiconductor memory device having a conventional center pad structure. Two rows of pads 11 and 12 are disposed at a center part of a die 10, and the pads are connected to a plurality of probes 15-1 to 15-N of a probe card, respectively. The two rows of pads 11 and 12 include a first row of pads 11 formed of a plurality of pads for a first channel 11-1 to 11-N, and a second row of pads 12 formed of a plurality of pads for a second channel 12-1 to 12-N.
The center pad structure is a pad structure in which a plurality of rows of pads are disposed at a center part of a die 10. Since recent semiconductor memory has been densely integrated to accomplish large storage capacity, a memory cell array region should be large. However, since a pad region is limited, the center pad structure is widely used to obtain a layout well matched with the memory cell array.
Hereinafter, functions of respective components and a wafer test method will be described.
A plurality of separated chips is disposed at a die 10 after completing the semiconductor wafer process. A plurality of internal circuits are integrated in the semiconductor memory device, and two rows of pads 11 and 12 are parallely disposed at a center part of the die 10.
The first row of pads 11 formed of a plurality of pads for a first channel 11-1 to 11-N are connected to several circuits of the internal circuits of the semiconductor memory device, and the second row of pads 12 formed of a plurality of pads for a second channel 12-1 to 12-N are connected to the other circuits, except for the several pads connected to the first channel pads 11-1 to 11-N, thereby transmitting and receiving a command signal, an address signal, a data signal, a control signal, and so on, to and from the exterior of the semiconductor chip.
A plurality of probes 15-1 to 15-N of the probe card are a plurality of long and sharp pins in direct contact with the two rows of pads 11 and 12 to input a desired signal generated from a tester (not shown), and receive a signal generated by the internal circuits to transmit the signal to the tester, thereby performing a failure analysis and a redundancy cell analysis of the semiconductor memory device.
At this time, the two rows of pads 11 and 12 are disposed at the center part of the die 10, and the plurality of first and second channel pads 11-1 to 11-N and 12-1 to 12-N are disposed in parallel with a certain pad size at predetermined pad pitches in two divided rows.
When the pads are disposed in a multi-row manner as shown in FIG. 1, since it is limiting to bond each pad to a lead end using a wire, the probe should be in contact with the wafer chip from both sides thereof, thus making it difficult to simultaneously test a plurality of chips.
In addition, since the bonding wire is formed at both sides of the chip, the probes 15-1 to 15-N of the probe card can hardly contact the chip after the wire bonding, thus making it difficult to measure the signal amplitude on a signal line and observe a waveform during development of a product.
That is, since the pad structure shown in FIG. 1 can hardly perform the wire bonding when the lead is not introduced in an upper or lower direction of the die 10, it is difficult to use the pad structure in a package for extracting the lead from one side of the chip such as a surface vertical package (SVP) or a zigzag in-line package (ZIP).
In addition, since the probes 15-1 to 15-N of the probe card should be in contact with both sides of the chip while probing the semiconductor chip in a wafer state, it is difficult to simultaneously test a plurality of chips. Further, since the bonding wire is formed at both sides of the chip after the wire bonding, it is difficult to contact the probes 15-1 to 15-N of the probe card with the chip, thus causing incorrect measurement of an internal signal.
In particular, since the micro bump pad has a pad size and a pad pitch substantially smaller than those of the pad used in the wafer probing of the conventional different packages, it is difficult to perform a wafer test using a probe card and it is impossible to perform various types of tests.